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nanoamp solutions, inc. 670 north mccarthy blvd. suite 220, milpitas, ca 95035 ph: 408-935-7777, fax: 408-935-7770 www.nanoamp.com N16D1618LPA stock no. 23395- rev l 1/06 1 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information 512k 16 bits 2 banks low power synchronous dram description these N16D1618LPA are low power 16,777,216 bits cmos synchronous dram organized as 2 banks of 524,288 words x 16 bits. these products are offering fully synchr onous operation and are referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. features ? jedec standard 1.8v power supply. ? auto refresh and self refresh. ? all pins are compatible with lvttl interface. ? 4k refresh cycle / 64ms. ? programmable burst length and burst type. - 1, 2, 4, 8 or full page for sequential burst. - 4 or 8 for in terleave burst. ? programmable cas latency : 2,3 clocks. ? programmable driver strength control. - full strength or 1/2, 1/4 of full strength ? deep power down mode ? all inputs and outputs re ferenced to the positive edge of the system clock. ? data mask function by dqm. ? internal dual banks operation. ? burst read single write operation. ? special function support. -pasr (partial array self refresh) -auto tcsr(temperature compensated self refresh) ? automatic precharge , includes concurrent auto precharge mode and controlled precharge table 1: ordering information part no. clock freq. temperature vdd/vddq interface package N16D1618LPAz2-75i 133mhz -25 o c to 85 o c 1.8v/1.8v lvttl 48-ball green fbga N16D1618LPAz2-10i 100mhz N16D1618LPAc2-60i 166mhz 60-ball green wbga N16D1618LPAc2-75i 133mhz N16D1618LPAc2-10i 100mhz N16D1618LPAt2-60i 166mhz 50-pin green tsop ii N16D1618LPAt2-75i 133mhz N16D1618LPAt2-10i 100mhz
N16D1618LPA stock no. 23395- rev l 1/06 2 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. figure 1: package confi guration (60ball wbga) note: 1. all dimensions in millimeters vss dq15 dq0 vdd dq14 vssq vddq dq1 dq13 vddq vssq dq2 dq12 dq11 dq4 dq3 dq10 vssq vddq dq5 dq9 vddq vssq dq6 dq8 nc nc dq7 nc nc nc nc nc udqm ldqm /we nc clk /ras /cas cke nc nc /cs a11 a9 nc nc a8 a7 a0 a10 a6 a5 a2 a1 vss a4 a3 vdd [bottom view] 7 6 5 4 3 2 1 0.65 3.9 10.1 0.1 6.4 0.1 9.1 1.0max 0.23 0.05 0.3 0.05 unit [mm] a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 [top view] 0.65 1.25 vss dq15 dq0 vdd dq14 vssq vddq dq1 dq13 vddq vssq dq2 dq12 dq11 dq4 dq3 dq10 vssq vddq dq5 dq9 vddq vssq dq6 dq8 nc nc dq7 nc nc nc nc nc udqm ldqm /we nc clk /ras /cas cke nc nc /cs a11 a9 nc nc a8 a7 a0 a10 a6 a5 a2 a1 vss a4 a3 vdd [bottom view] 7 6 5 4 3 2 1 0.65 3.9 10.1 0.1 6.4 0.1 9.1 1.0max 0.23 0.05 0.3 0.05 unit [mm] a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 [top view] 0.65 1.25
N16D1618LPA stock no. 23395- rev l 1/06 3 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. figure 2: package configur ation (48balls fbga) note: 1. all dimensions in millimeters [bottom view] [top view] clk /cs a0 a1 a2 /cas dq8 nc a3 a4 cke dq0 dq9 dq10 a5 a6 dq1 dq2 vss dq11 /ras a7 dq3 vddq vdd dq12 nc nc dq4 vssq dq14 dq13 nc nc dq5 dq6 dq15 nc udqm ldqm /we dq7 nc a8 a9 a10 a11 nc a b c d e f g h 1 2 3 4 5 6 a b c d e f g h 6 5 4 3 2 1 8 0.1 5.25 0.75 6.0 0.1 3.75 0.75 0.23 0.05 0.30 0.05 1.0max 1.125 unit [mm]
N16D1618LPA stock no. 23395- rev l 1/06 4 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. figure 3: package configur ation (50 pin tsop ii) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 50 pin tsop ii 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 vdd dq0 dq1 gndq dq2 dq3 vddq dq4 dq5 gndq dq6 dq7 vddq ldqm /we /cas /ras /cs a11 a10 a0 a1 a2 a3 vdd gnd dq15 dq14 gndq dq13 dq12 vddq dq11 dq10 gndq dq9 dq8 vddq nc udqm clk cke nc a9 a8 a7 a6 a5 a4 gnd 20.95 0.10 10.16 0.10 0.80 bsc 0 o - 8 o [top view] 11.76 0.20 1.20 max 0.50 0.10 notes: 1. all dimensions in millimeters unless otherwise noted 2. bsc = basic lead spacing between centers 3. max / min 0.49 0.27 0.15 0.05 1.00 0.05 0.17 nom 0.80 nom 1.03 max
N16D1618LPA stock no. 23395- rev l 1/06 5 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. table 2: pin descriptions pin pin name descriptions clk system clock the system clock input. all other inputs are registered to the sdram on the rising edge of the clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh. /cs chip select enable or disable all inputs except clk, cke and dqm a11 bank address selects bank to be activated during /ras activity selects bank to be read/written during /cas activity a0~a10 address row address : ra0~ra10 column address: ca0~ca7 auto precharge : a10 /ras, /cas, /we row address strobe, column address strobe, write enable /ras, /cas and /we define the operation refer function truth table for details ldqm/udqm data input/output mask controls output buffers in re ad mode and masks input data in write mode dq0~dq15 data input/output multiplexed data input/output pin vdd/vss power supply/ground power supply for internal circuits and input buffers vddq/vssq data output power/ground power supply for output buffers nc no connection no connection
N16D1618LPA stock no. 23395- rev l 1/06 6 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. figure 4: functional block diagram tcsr pasr control logic command decoder column address buffer & burst counter clock generator clk cke row address buffer & refresh counter /cs /ras /cas /we mode register bank b row decoder bank b row decoder bank a row decoder sense amplifier column decoder & latch circuit bank a row decoder sense amplifier column decoder & latch circuit dq dqm address data control circuit data control circuit latch circuit latch circuit input & output buffer input & output buffer extended mode register
N16D1618LPA stock no. 23395- rev l 1/06 7 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. figure 5: simplified state diagram cke cke cke cke idle row active self refresh cbr refresh power down active power down read write read a write a pre- charge read suspend read a suspend write suspend write a suspend power on mode register set precharge cke cke cke cke cke cke cke cke cke cke cke cke read write cke cke cke cke read write a u t o p r e c h a r g e w r i t e w i t h a u t o p r e c h a r g e w r i t e w i t h a u t o p r e c h a r g e w r i t e w i t h pre b s t b s t act c k e c k e c k e c k e ref s e l f s e l f e x i t s e l f s e l f e x i t mrs p r e ( p r e c h a r g e t e r m i n a t i o n ) p r e ( p r e c h a r g e t e r m i n a t i o n ) automatic sequence manual input automatic sequence manual input extended mode register set e m r s deep power down d pd e x i t d pd
N16D1618LPA stock no. 23395- rev l 1/06 8 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. figure 6: mode re gister definition note: m11(a11) must be sest to ?0? to select mode register (vs. the extend mode register) burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 3 . note : 1. for full-page accesses: y = 256 2. for a burst length of two, a1-a7 select the block-of- two burst; a0 selects the starting column within the block. 3. for a burst length of four , a2-a7 select the block-of- four burst; a0-a1 select the starting column within the block. 4. for a burst length of eigh t, a3-a7 select the block-of- eight burst; a0-a2 select th e starting column within the block. 5. for a full-page burst, the fu ll row is selected and a0- a7 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a7 select the unique column to be accessed, and mode register bit m3 is ignored. wb burst read and single write 1 burst read and burst write 0 write burst mode m9 burst read and single write 1 burst read and burst write 0 write burst mode m9 interleave 1 sequential 0 burst type m3 interleave 1 sequential 0 burst type m3 reserved 0 0 1 reserved 1 0 1 2 0 1 0 1 1 0 0 3 1 1 0 reserved 0 1 1 reserved 1 1 1 reserved 0 0 0 cas latency m4 m5 m6 reserved 0 0 1 reserved 1 0 1 2 0 1 0 1 1 0 0 3 1 1 0 reserved 0 1 1 reserved 1 1 1 reserved 0 0 0 cas latency m4 m5 m6 full page reserved reserved reserved 8 4 2 1 m3 = 0 burst length reserved 0 0 1 reserved 1 0 1 4 0 1 0 2 1 0 0 8 1 1 0 reserved 0 1 1 reserved 1 1 1 1 0 0 0 m3 = 1 m0 m1 m2 full page reserved reserved reserved 8 4 2 1 m3 = 0 burst length reserved 0 0 1 reserved 1 0 1 4 0 1 0 2 1 0 0 8 1 1 0 reserved 0 1 1 reserved 1 1 1 1 0 0 0 m3 = 1 m0 m1 m2 0 cas latency bt burst length address bus 0 1 2 3 4 5 6 10987 11 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 mode register (mx) 00 0 table 3: burst definition burst length starting column address order of access within a burst a2 a1 a0 sequential interleave 2 0 0-1 0-1 1 1-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page n=a0~7 (location 0-256) c n , c n+1 . c n+2 , c n+3 , c n+4 ? ?c n-1 , c n ... not supported
N16D1618LPA stock no. 23395- rev l 1/06 9 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. figure 7: extended mode register note: 1. e11(a11) must be set to ?1? to select extend mode register (vs. the base mode register) 1 pasr address bus extended mode register (ex) 0 1 2 3 4 5 6 10987 11 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 reserved 0 0 1 half of one bank (a11=0, row address msb=0) 1 0 1 reserved 1 1 0 quarter of one bank (a11=0, row address 2 msb=0) 0 1 1 one bank (a11=0) 1 0 0 reserved 0 1 0 reserved 1 1 1 all banks 0 0 0 self refresh coverage e0 e1 e2 reserved 0 0 1 half of one bank (a11=0, row address msb=0) 1 0 1 reserved 1 1 0 quarter of one bank (a11=0, row address 2 msb=0) 0 1 1 one bank (a11=0) 1 0 0 reserved 0 1 0 reserved 1 1 1 all banks 0 0 0 self refresh coverage e0 e1 e2 1/2 strength 1 0 1/4 strength 0 1 reserved 1 1 full strength 0 0 driver strength e5 e6 1/2 strength 1 0 1/4 strength 0 1 reserved 1 1 full strength 0 0 driver strength e5 e6 0 00 0 ds tcsr 70 1 0 45 0 1 auto 1 1 85 0 0 maximum case temp. e3 e4 70 1 0 45 0 1 auto 1 1 85 0 0 maximum case temp. e3 e4
N16D1618LPA stock no. 23395- rev l 1/06 10 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. functional description in general, this 16mb sdram (512k x 16bits x 2banks) is a dual-bank dram that operates at 1.8v and includes a synchronous interface (all signals are registered on the pos itive edge of the clock signal, clk). each of the 8,388,608- bit banks is organized as 2,048 rows by 256 columns by 16-bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and conti nue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an acti ve command, which is then followed by a read or write command. the address bits registered coincident with t he active command are used to select the bank and row to be accessed (a11 select the bank, a0-a10 select the row). the address bits (a11 select the bank, a0-a7 select the column) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. power up and initialization sdrams must be powered up and initialized in a predefin ed manner. operational procedures other than those specified may result in undefined operation. once power is applied to vdd and vddq(simultaneously) and the clock is stable(stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a comma nd inhibit or nop. cke must be held high during the entire initialization period until the re charge command has been issued. starting at some point during this 100s period and continuing at least thro ugh the end of this peri od, command inhibit or nop commands should be applied. once the 100s delay has bee n satisfied with at least one command inhibit or nop command having been applied, a precharge command shoul d be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles mu st be performed. after the auto refresh cycles are complete, the sdram is ready for mode register progra mming. because the mode register will power up in an unknown state, it should be loaded prior to applying an y operational command. and a extended mode register set command will be issued to program specific mode of self re fresh operation(pasr). the following these cycles, the low power sdram is ready for normal operation. register definition mode register the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an opera ting mode and a write burst mode. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or interleaved), m4-m6 specif y the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 should be set to zero. m11 should be set to zero to prevent extended mode register. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. extended mode register the extended mode register controls the functions beyond those controlled by the mode register. these additional functions are special features of the batram device. they include tem perature compensated self refresh (tcsr) control, and partial array self refresh (pasr) and driver strength (ds). the extended mode register is programmed via the mode register set command (a11=1) and retains the stored information until it is programmed again or the device loses power. the extended mode register must be pr ogrammed with e7 through e10 set to ?0?. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before before initiating any subsequent oper ation. violating either of t hese requirements results in unspecified operation.
N16D1618LPA stock no. 23395- rev l 1/06 11 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 1. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is availabl e for the sequential type. the full-page burst is used in conjunction with the burst terminate comm and to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility wit h future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effect ively selected. all accesses for that burst take place within this bloc k, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a7 when the burst length is set to two; by a2-a7 when the burst length is set to four; and by a3-a7 when the burst length is set to eight. the re maining (least significant) address bit(s) is (are) used to select the starting location within the block. full-p age bursts wrap within the page if the boundary is reached. bank(row) active the bank active command is used to activate a row in a specified bank of the device. th is command is initiated by activating /cs, /ras and deasserting /cas, /we at the positive edge of the clock. the value on the a11 selects the bank, and the value on the a0-a10 selects the row. this row remains active for column access until a precharge command is issued to that bank. read and write operations can only be initiat ed on this activated bank after the minimum trcd time is passed from the activate command. read the read command is used to initiate t he burst read of data. this command is initiated by activating /cs, /cas, and deasserting /we, /ras at the positive edge of the clock. a11 input select the bank, a0-a7 address inputs select the starting column location. the value on input a10 determines wh ether or not auto precharge is used. if auto precharge is selected the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain active for subsequent accesses. the leng th of burst and the cas latency will be determined by the values programmed during the mrs command. write the write command is used to initiate the burst write of data. this command is initiated by activating /cs, /cas, /we and deasserting /ras at the positive edge of the clock. a1 1 input select the bank, a0-a7 address inputs select the starting column location. the value on input a10 determines wh ether or not auto precharge is used. if auto precharge is selected the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain active for subsequent accesses.
N16D1618LPA stock no. 23395- rev l 1/06 12 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. cas latency the cas latency is the delay, in clock cycles, between t he registration of a read command and the availability of the first piece of output data. the latency c an be set to two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. the dqs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the la tency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 2. re served states should not be used as unknown operation or incompatibility with future versions may result. figure 8: cas latency operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the program med burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but wr ite accesses are single-loc ation (nonburst) accesses. clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=2 t3 read clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=2 t3 read clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=3 t3 nop t4 read don?t care undefined clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=3 t3 nop t4 read don?t care undefined
N16D1618LPA stock no. 23395- rev l 1/06 13 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. note : 1. cken is the logic state of cke at clock edge n; ck en-1 was the state of cke at the previoys clock edge. h: high level, l: low level, x: don't care, v: valid 2. exiting self refresh occurs by asynchronously bringing cke from low to high and will put the device in the all banks idle st ate once txsr is met. command inhibit or nop commands should be i ssued on any clock edges occuring dur ing the txsr period. a mimum of two nop commands must be provided during txsr period. 3. during refresh operation, internal refr esh counter controls row addressing; all in puts and i/os are ?don?t care? except for cke. 4. a0-a10 define op code written to the mode register, and a11 must be issued 0 in the mode register set, and 1 in the extended mode register set. 5. dqm ?l? means the data write/ouput enable and ?h? means the write inhibit/output high-z. write dqm latency is 0 clk and read dqm latency is 2 clk. 6. standard sdram parts assign this command sequence as burst te rminate. for bat ram parts, the burst terminate command is assigned to the deep power down function. table 4: command truth table command cken-1 cken cs ras cas we dqm addr a10 note command inhibit (nop) h x h x x x x x no operation (nop) h x l h h h x x mode register set h x l l l l x op-code 4 extended mode register set h x l l l l x op-code 4 active (select bank and activate row) h x l l h h x bank/row read h x l h l h l/h bank/col l 5 read with autoprecharge h x l h l h l/h bank/col h 5 write h x l h l l l/h bank/col l 5 write with autoprecharge h x l h l l l/h bank/col h 5 precharge all banks h x l l h l x x h precharge selected bank h x l l h l x bank l burst stop h h l h h l x x auto refresh h h l l l h x x 3 self refresh entry h l l l l h x x 3 self refresh exit l h hx x x xx2 lh hh precharge power down entry h l hx x x xx lh hh precharge down exit l h hx x x xx lh hh clock suspend entry h l hx x x xx lv vv clock suspend exit l h x x x deep power down entry h l l h h l x x 6 deep power down exit l h x x x
N16D1618LPA stock no. 23395- rev l 1/06 14 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. table 5: function truth table current state command action note /cs /ras /cas /we a11 a0-a10 description idle l l l l op code mode register set set the mode register 14 l l l h x x auto or self refresh start auto or self refresh 5 l l h l ba x precharge no operation l l h h ba row addr bank active activate the specific bank and row l h l l ba col addr/a10 write/write ap illegal 4 l h l h ba col addr/a10 read/read ap illegal 4 lh hhxx nop nop 3 h x x x x x device deselect nop or power down 3 row active l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge precharge 7 l l h h ba row addr bank active illegal 4 l h l l ba col addr/a10 write/write ap start write : optional ap(a10 = h) 6 l h l h ba col addr/a10 read/read ap start read: optional ap(a10 = h) 6 lh hhxx nop nop h x x x x x device deselect nop read l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge termination burst : start the precharge l l h h ba row addr bank active illegal 4 l h l l ba col addr/a10 write/write ap termination burst: start write(ap) 8,9 l h l h ba col addr/a10 read/read ap termination burst: start read(ap) 8 l h h h x x nop continue the burst h x x x x x device deselect continue the burst write l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge termination burst : start the precharge l l h h ba row addr bank active illegal 4 l h l l ba col addr/a10 write/write ap termination burst: start write(ap) 8,9 l h l h ba col addr/a10 read/read ap termination burst: start read(ap) 8 l h h h x x nop continue the burst h x x x x x device deselect continue the burst
N16D1618LPA stock no. 23395- rev l 1/06 15 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. read with auto pre- charge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row addr bank active illegal 4,12 l h l l ba col addr/a10 write/write ap illegal 12 l h l h ba col addr/a10 read/read ap illegal 12 l h h h x x nop continue the burst h x x x x x device deselect continue the burst write with auto pre- charge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row addr bank active illegal 4,12 l h l l ba col addr/a10 write/write ap illegal 12 l h l h ba col addr/a10 read/read ap illegal 12 l h h h x x nop continue the burst h x x x x x device deselect continue the burst pre- charg- ing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge no operation: bank(s) idle after trp l l h h ba row addr bank active illegal 4,12 l h l l ba col addr/a10 write/write ap illegal 4,12 l h l h ba col addr/a10 read/read ap illegal 4,12 lh hhxx nop no operation: bank(s) idle after trp h x x x x x device deselect no operation: bank(s) idle after trp row activat- ing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row addr bank active illegal 4, 11, 12 l h l l ba col addr/a10 write/write ap illegal 4,12 l h l h ba col addr/a10 read/read ap illegal 4,12 lh hhxx nop no operation: row acti- vated after trcd h x x x x x device deselect no operation: row acti- vated after trcd table 5: function truth table current state command action note /cs /ras /cas /we a11 a0-a10 description
N16D1618LPA stock no. 23395- rev l 1/06 16 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. write recov- ering l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row addr bank active illegal 4,12 l h l l ba col addr/a10 write/write ap start write : optional ap(a10 = h) l h l h ba col addr/a10 read/read ap start write : optional ap(a10 = h) 9 lh hhxx nop no operation : row active after tdpl h x x x x x device deselect no operation : row active after tdpl write recover- ing with auto pre- charge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row addr bank active illegal 4,12 l h l l ba col addr/a10 write/write ap illegal 4,12 l h l h ba col addr/a10 read/read ap illegal 4,9, 12 lh hhxx nop no operation : precharge after tdpl h x x x x x device deselect no operation : precharge after tdpl refres hing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row addr bank active illegal 13 l h l l ba col addr/a10 write/write ap illegal 13 l h l h ba col addr/a10 read/read ap illegal 13 lh hhxx nop no operation : idle after trc h x x x x x device deselect no operation : idle after trc mode register accessing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row addr bank active illegal 13 l h l l ba col addr/a10 write/write ap illegal 13 l h l h ba col addr/a10 read/read ap illegal 13 lh hhxx nop no operation : idle after 2 clock cycle h x x x x x device deselect no operation : idle after 2 clock cycle table 5: function truth table current state command action note /cs /ras /cas /we a11 a0-a10 description
N16D1618LPA stock no. 23395- rev l 1/06 17 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. note : 1. h: logic high, l: logic low, x: don't ca re, ba: bank address, ap: auto precharge. 2. all entries assume that cke was active during the pr eceding clock cycle. 3. if both banks are idle and cke is inactive, then in power down cycle 4. illegal to bank in specified states. function ma y be legal in the bank indicated by bank address, depending on the state of that bank. 5. if both banks are idle and cke is inactive, then self refresh mode. 6. illegal if trcd is not satisfied. 7. illegal if tras is not satisfied. 8. must satisfy burst interrupt condition. 9. must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. must mask preceding data which don't satisfy tdpl. 11. illegal if trrd is not satisfied 12. illegal for single bank, but legal for other banks in multi-bank devices. 13. illegal for all banks. 14. mode register set and extended mode register set is same command truth table except a11.
N16D1618LPA stock no. 23395- rev l 1/06 18 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. table 6: cke truth table current state cke command action note prev cycle current cycle /cs /ras /cas /we a11 a0-a10 self refresh hxxxxxxxinvalid 2 lhhxxxxx exit self refresh with device deselect 3 lhlhhhxx exit self refresh with no operation 3 l h l h h l x x illegal 3 l h l h l x x x illegal 3 l h l l x x x x illegal 3 l l x x x x x x maintain self refresh power down hxxxxxxxinvalid 2 lh hx xxx x power down mode exit, all banks idle 3 lh hhx x lhl lxxx x illegal 3 xlxx x xxlx x llxxxxxx maintain power down mode deep power down hxxxxxxxinvalid 2 lhxxxxxx deep power down mode set 6 llxxxxxx maintain deep power down mode all bank idle hhhxxx refer to the idle state section of the current state truth table 4 hhlhxx 4 hhllhx 4 h h l l l h x x auto refresh h h l l l l op-code mode register set 5 hlhxxx refer to the idle state section of the current state truth table 4 hllhxx 4 hlllhx 4 h l l l l h x x entry self refresh 5 h l l l l l op-code mode register set l x x x x x x x power down 5 any state other than listed above hhxxxxxx refer to operations of the current state truth table hlxxxxxx begin clock suspend next cycle lhxxxxxx exit clock suspend next cycle llxxxxxx maintain clock sus- pend
N16D1618LPA stock no. 23395- rev l 1/06 19 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. note : 1. h: logic high, l: logic low, x: don't care 2. for the given current state cke must be low in the previous cycle. 3. when cke has a low to high transition, the clock and other i nputs are re-enabled asynchronously. when exiting power down mod e, a nop (or device deselect) command is required on the first positive edge of clock after cke goes high. 4. the address inputs depend on the command that is issued. 5. the precharge power down mode, the self refresh mode, and the mode register set can only be entered from the all banks idle state. 6. when cke has a low to high transition, the clock and other inputs are re-enabled asynchronou sly. when exiting deep power dow n mode, a nop (or device deselect) command is required on t he first positive edge of clock after cke goes high and is maintai ned for a minimum 100usec.
N16D1618LPA stock no. 23395- rev l 1/06 20 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. note : 1. stresses greater than those listed under ?absolute maximu m ratings? may cause permanent dam age to the device. this is a stress rating only, and functional operation of the device at these or any other c onditions above those indicated in the operat ional sections of this specification is not implied. exposure to abs olute maximum rating conditions for extended periods may affect r eli- ability. note : 1. vddq must not exceed the level of vdd 2. vih(max) = vddq+1.5v ac. the overshoot voltage duration is 3ns 3. vil(min) = -1.0v ac. the overshoot voltage duration is 3ns. 4. any input 0v vin vddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs 5. dout is disabled, 0v vout vddq. table 7: absolute maximum rating parameter symbol rating unit ambient temperature (industrial) ta -25 ~ 85 c ambient temperature (commerical) 0 ~ 70 storage temperature tstg -55~150 c voltage on any pin relative to vss vin, vout -1.0~2.6 v voltage on vdd relative to vss vdd, vddq -1.0~2.6 v short circuit output current ios 50 ma power dissipation pd 1 w table 8: capacitance (ta = 25c, f = 1mhz, vdd = 1.8v) parameter pin symbol min max unit input capacitance clk cl1 2 4 pf a0~a11, cke, /cs /ras, /cas, /we, l(u)dqm cl2 2 4 pf data input / output capacitance dq0~dq15 cio 3 5 pf table 9: dc characteristi c & operation condition (ta = -25 to 85c) parameter symbol min typ max unit note power supply voltage vdd 1.65 1.8 1.95 v vddq 1.65 1.8 1.95 v 1 input high voltage vih 0.8vddq -- vddq+0.3 v 2 input low voltage vil -0.3 0 0.3 v 3 output logic high current voh 0.9vddq -- -- v ioh = -0.1ma output logic low current vol -- -- 0.2 v iol = +0.1ma input leakage current ili -1 -- 1 a 4 output leakage current ilo -1.5 -- 1.5 a 5
N16D1618LPA stock no. 23395- rev l 1/06 21 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. table 10: ac oper atng condition (ta = -25 to 85c, vdd=1.8v 0.15v, vss = 0v) parameter symbol typ unit ac input high / low level voltage vih / vil 0.9 vddq / 0.2 v input timing measurement reference level voltage vtrip 0.5 vddq v input rise / fall time tr / tf 1 / 1 ns output timing measurement reference level voutref 0.5 vddq v output load capacitance for access time measurement cl 30 pf output 500 ? 500 ? vddq 30pf output 30pf 50 ? vtt=0.5 x vddq z0=50 ? dc output load circuit ac output load circuit
N16D1618LPA stock no. 23395- rev l 1/06 22 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information nanoamp solutions, inc. note: 1. measured with outputs open. 2. refresh period is 64ms. table 11: dc characteristic (dc operating conditions unless otherwise noted) parameter sym test condition speed unit note 60 75 10 operating current icc1 burst length=1, one bank active trc trc (min) iol=0ma 35 ma 1 precharge standby current in power down mode icc2p cke vil (max), tck=10ns 60 ua -- icc2ps cke & clk vil(max), tck= 60 ua -- precharge standby current in non power down mode icc2n cke vih (min), /cs vih(min), tck=10ns input signal are changed one time during 2clks. 6ma-- icc2ns cke vih (min), /cs vih(min) tck= input signals are stable 1ma-- active standby current in power- down mode icc3p cke vil(max), tck=10ns 0.5 ma -- icc3ps cke & clk vil(max), tck= 0.5 ma -- active standby current in non power-down mode icc3n cke vih(min), /cs vih(min), tck=10ns input signals are changed one time during 2clks 12 ma -- icc3ns cke vih(min), clk vil(max) tck= input signals are stable 6ma-- operating current (burst mode) icc4 tck tck(min), iol=0ma, page burst all banks activated, tccd = 1clk 55 45 35 ma 1 auto refresh current icc5 trc trfc (min) all banks active 30 ma 2 self refresh current pasr tcsr icc6 cke 0.2v ua 2bank 45~85c 65 ~ 80 -25~45c 50 ~ 65 1bank 45~85c 60 ~ 75 -25~45c 45 ~ 60 deep power down mode current icc7 5ua
stock no. 23395- rev l 1/06 23 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. N16D1618LPA advance information table 12: ac characteristic (ac operating conditions unless otherwise noted) parameter sym -60 -75 -10 unit note min max min max min max clk cycle time cl=3 tck3 6.0 1000 7.5 1000 10 1000 ns 1 cl=2 tck2 10 10 10 access time from clk (pos. edge) cl=3 tac3 5.5 6 8 2 cl=2 tac2 888 clk high-level width tch 2.5 2.5 2.5 3 clk low-level width tcl 2.5 2.5 2.5 3 cke setup time tcks 1.5 2.0 2.0 cke hold time tckh 1.0 1.0 1.0 /cs, /ras, /cas, /we, dqm setup time tcms 1.5 2.0 2.0 /cs, /ras, /cas, /we, dqm hold time tcmh 1.0 1.0 1.0 address setup time tas 1.5 2.0 2.0 address hold time tah 1.0 1.0 1.0 data-in setup time tds 1.5 2.0 2.0 data-in hold time tdh 1.0 1.0 1.0 data-out high-impedance time from clk (pos.edge) cl=3 thz3 5.5 6 8 4 cl=2 thz2 8 8 8 data-out low-impedance time tlz 1.0 1.0 1.0 data-out hold time (load) toh 2.5 2.5 2.5 data-out hold time (no load) tohn 1.8 1.8 1.8 active to precharge command tras 42 100k 45 100k 40 100k precharge command period trp 18 22.5 20 active bank a to active bank a com- mand trc 60 67.5 60 5 active bank a to active bank b com- mand trrd 12 15 20 active to read or write delay trcd 18 22.5 20 read/write command to read/write command tccd 111clk6 write command to input data delay tdwd 000clk6 data-in to precharge command tdpl 12 15 20 ns 7 data-in to active command tdal 30 37.5 40 7 dqm to data high-impedance during reads tdqz 222 clk 6 dqm to data mask during writes tdqm 000 6 load mode register command to active or refresh command tmrd 222 8 data-out to high-impedance from precharge command cl=3 troh3 333 6 cl=2 troh2 222 last data-in to burst stop command tbdl 111 6 last data-in to new read/write com- mand tcdl 111 6 cke to clock disable or power-down entry mode tcked 111 9 cke to clock enable or power-down exit setup mode tped 111 9 self refresh exit time tsre 111 10
stock no. 23395- rev l 1/06 24 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. N16D1618LPA advance information note: 1. the clock frequency must remain const ant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including tdpl, and precharge commands). cke may be used to reduce the data rate. 2. tac at cl = 3 with no load is 5.5ns and is guaranteed by des ign. access time to be measured with input signals of 1v/ns ed ge rate, from 0.8v to 0.2v. if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter. 3. ac characteristics assume tt = 1ns. if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter. 4. thz defines the time at which the output achieves the open circuit condition; it is not a re ference to voh or vol. the las t valid data element will meet toh before going high-z. 5. parameter guaranteed by design. a. target values listed wi th alternative values in parentheses. b. trfc must be less than or equal to trc+1clk txsr must be less than or equal to trc+1clk 6. required clocks are specified by jedec f unctionality and are not dependent on any timing parameter. 7. timing actually specified by tdpl plus trp; clock( s) specified as a reference only at minimum cycle rate 8. jedec and pc100 specify three clocks. 9. timing actually specified by tcks; clock(s) specified as a re ference only at minimum cycle rate. 10. a new command can be given trc after self refresh exit. refresh period (4,096 rows) tref 64 64 64 ms auto refresh period trfc 66 67.5 70 ns 5 exit self refresh to active command txsr 66 67.5 70 5 transition time tt 0.5 1.2 0.5 1.2 0.5 1.2 table 12: ac characteristic (ac operating conditions unless otherwise noted) parameter sym -60 -75 -10 unit note min max min max min max
stock no. 23395- rev l 1/06 25 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. N16D1618LPA advance information special operation for low power consumption temperature compensated self refresh temperature compensated self refresh allows the controller to program t he refresh interval during self refresh mode, according to the case temperature of the low powe r sdram device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme temperatures would the controller have to select a tcsr level that will guarantee dat a during self refresh. every cell in the dram requires refreshing due to the capacitor losing its charge over time . the refresh rate is dependent on temperature. at higher temperatures a capacitor loses charge quicker than at lowe r temperatures, requiring the cells to be refreshed more often. historically, during self refresh, the refresh ra te has been set to accommodate the worst case, or highest temperature range expected. thus, during ambient temperatures, the power consumed du ring refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. setting e4 and e3, allow the dram to accommodate more specific temperature regions during self refresh. there are four temperat ure settings, which will vary the self refresh current according to the selected temperature. this selectable refresh rate will save power when the dram is operating at normal temperatures. partial array self refresh for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are two bank;all two banks, one bank;bank a. write and read commands can still occur du ring standard operation, but only the selected banks will be refreshed during self refresh. data in banks that are disabled will be lost. deep power down deep power down is an operating mode to achieve maximu m power reduction by eliminating the power of the whole memory array of the devices. data will not be retained onc e the device enters deep power down mode. this mode is entered by having all banks idle then /cs and /we held low with /ras and /cas held high at the rising edge of the clock, while cke is low. this mode is exited by asserting cke high.
stock no. 23395- rev l 1/06 26 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. N16D1618LPA advance information figure 9: deep power down mode entry figure 10: deep powe r down mode exit clk cke /cs /ras prechar g e if needed deep power down entry trp clk cke /cs /ras prechar g e if needed deep power down entry trp clk cke /cs /ras /cas /we 100 s trp trfc deep power down exit all banks prechar g e auto refresh mode register set extended mode re g ister set new command auto refresh clk cke /cs /ras /cas /we 100 s trp trfc deep power down exit all banks prechar g e auto refresh mode register set extended mode re g ister set new command auto refresh
stock no. 23395- rev l 1/06 27 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. N16D1618LPA advance information ordering information ? 2004 - 2005 nanoamp solutions, inc. all rights reserved. nanoamp solutions, inc. ("nanoamp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. nanoamp does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. nanoamp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does nanoamp ass ume any liability arising out of the application or use of any product or circuit described herein. nanoamp does not authorize use of its products as critical components in any application in which the failure of the nanoamp product may be expected to result in significant injury or de ath, including life support systems and critical medical instrumen t. revision history revision date change description a november 18, 2004 initial advance release b november 30, 2004 changed refresh time to 4k / 64ms c december 15, 2004 general update. added bga package option d february 16, 2005 changed driver strength control emrs table e february 23, 2005 changed pin ordering (page 2) changed pin name ba to a11 f march 1, 2005 removed 2/3 reg drive strength (page 1) updated extend mode register diagram (page 8) modifed pin name description (page 10) updated command truth table (burst stop). changed cken ?x? to ?h? (page 12) updated partial array description. changed bank 0 to bank a (page 24) g march 3, 2005 updated mode register and extended mode register diagram (page 7, 8, 9, 24) fixed typo in table 3 (page 7) updated footnote #14(page 16) deleted tsre from ac timing table and footnote #10 (page 22, 23) h may 3, 2005 changed 48fbga and 60wbga package thickness to 1.0mm max added pb-free ordering option for 48fbga package and 60wbga package i may 11, 2005 changed 48fbga package option to green instead of pb-free. j june 14, 2005 added 50-pin tsop ii package option k august 15, 2005 updated ac/dc characteristics and added green tsop ii l january 2006 designated green package to be rohs compliant n 16 d 16 18 lp a xx - xx x nanoamp solutions product type density data i/o width power supply temperature package speed generation features 16= 16mb d = sdram 16=16i/o 18 = 1.8v lp = low power sdram a = 1st generation 60 = 6.0ns (166mhz) 75 = 7.5ns (133mhz) 10 = 10ns (100mhz) c = commercial (0-70c) i = industrial (-25 to 85) z2 = green 48fbga (rohs compliant) c2 = green 60wbga (rohs compliant) t2 = green 50 tsop2 (rohs compliant)

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